S3CC9ED advanced information publication number 00-s3-cc9ed march 2002 ( rev.0 ) cmos microcontroller for smart card applications 1 overview the S3CC9ED single-chip cmos micro-controller is designed for low voltage smart card applications and is fabricated using an advanced 0.18-micron cmos process. its fast and reliable 16-bit cpu is based on the smart card-purpose calmrisc16 processor. features cpu 16-bit calmrisc16 cpu core memory allocation 384k bytes rom 128k bytes eeprom 8k bytes static ram memory protection unit eeprom operations 1 to 128 bytes eeprom erase/write operations 2.0 ms fast erase/write time 500k erase/write cycles (minimum) 50 years data retention (minimum) data security 128 bytes write protected security area 128 bytes of non erasable eeprom reset operations are selective if abnormal condition is detected. des/t-des built-in hardware des/t-des circuit for prevent spa/dpa interrupts four interrupt sources and vectors (fiq, irq, swi) clock sources external : 1mhz ? 5mhz internal variable clock : 10mhz+-10%(vdd=5v) serial i/o interface hardware uart for handing serial interface in accordance with iso 7816 communication protocols random number generator one 16-bit random number generator start and stop control memory protection unit read/write access controllable base/limit region registers : 8 sets configurable range : 4-mbyte areas with 128- byte resolution. all the controls can be done at privilege mode bus scrambling ram bus scrambling with random number eeprom bus scrambling with user defined seed security detector many kind of security detectors timers 16-bit timer with 8 bit prescaler one 20-bit watchdog timer operating characteristics single power supply: 1.62 to 5.5 v operating frequency: 1 to 5 mhz operating temperature: -25 c to +85 c package 8-pin cob (conforms to iso standard 7816)
S3CC9ED advanced information 2 block diagram address and data bus cpu (calmrisc16) rom 384-kbyte eeprom 128-kbyte i/o (h/w uart) r.n.g. (note) 16-bits note: r.n.g. means random number generator. sio power-on reset hardware detectors timers (16 bit timer/ 20 bit wdt) clock ram 8-kbyte scrambling circuit mpu figure 1. block diagram electrical data (t a = ? 25 c to + 85 c, v dd = 1.62 v to 5.5 v) parameter symbol conditions min typ max unit supply current i dd1 f clk = 5 mhz, 5.5 v ? ? 10 ma f clk = 4 mhz, 3.3 v ? ? 6 stop current i dd2 f clk = 1 mhz, 5.5 v ? ? 200 a i dd3 f clk = gnd, 5.5 v ? ? 100 a table 1. electrical characteristics
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